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PRELIMINARY
CY22E016L
16-Kbit (2K x 8) nvSRAM
Features
* 25 ns, 35 ns and 45 ns Access Times * "Hands-off" Automatic STORE on Power Down with external 68F capacitor * STORE to QuantumTrap(R) Nonvolatile Elements is initiated by Hardware or Autostore(R)on Power-down * RECALL to SRAM Initiated on Power-up * Infinite READ, WRITE and RECALL Cycles * 10 mA Typical ICC at 200 ns Cycle Time * 1,000,000 STORE Cycles to QuantumTrap * 100-Year Data Retention to QuantumTrap * Single 5V Operation +10% * Commercial, Industrial Temperature * SOIC Package * RoHS Compliance
Functional Description
The Cypress CY22E016L is a fast static RAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an infinite number of times, while independent, nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down. A 68-F or larger capacitor tied from VCAP to ground guarantees the STORE operation, regardless of power-down slew rate or loss of power from "hot swapping". Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. A hardware STORE may be initiated with the HSB pin.
Logic Block Diagram
V CC V CAP
Quantum Trap 32 X 512
A5 A6 A7 A8 A9
STORE
POWER CONTROL STORE/ RECALL CONTROL
ROW DECODER
STATIC RAM ARRAY 32 X 512
RECALL
HSB
DQ 0 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
COLUMN I/O
INPUT BUFFERS
DQ 1
COLUMN DEC
A 0 A 1 A 2 A 3 A 4 A 10
OE
CE WE
Cypress Semiconductor Corporation Document #: 001-06727 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised November 28, 2006
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PRELIMINARY
Pin Configurations
CY22E016L
V CAP NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 V SS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24
V CC WE HSB A8 A9 NC OE A 10 CE DQ7 DQ6 DQ5 DQ4 DQ3
28-SOIC
Top View
(Not To Scale)
23 22 21 20 19 18 17 16 15
Pin Definitions
Pin Name A0-A10 WE CE OE VSS VCC HSB I/O Type Input Input Input Input Ground Description Address Inputs used to select one of the 2,048 bytes of the nvSRAM. Write Enable Input, active LOW. When selected LOW, enables data on the I/O pins to be written to the address location latched by the falling edge of CE. Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the I/O pins to tri-state. Ground for the device. Should be connected to ground of the system.
DQ0-DQ7 Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation.
Power Supply Power Supply inputs to the device. Input/Output Hardware Store Busy. When low this output indicates a Hardware Store is in progress. When pulled low external to the chip it will initiate a nonvolatile STORE operation. A weak internal pull-up resistor keeps this pin high if not connected. (Connection Optional) Power Supply Autostore(R) Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. No Connect No Connects. This pin is not connected to the die
VCAP NC
Document #: 001-06727 Rev. *C
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PRELIMINARY
Device Operation
The CY22E016L nvSRAM is made up of two functional components paired in the same physical cell. These are a SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The CY22E016L supports infinite reads and writes just like a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 1 million STORE operations.
CY22E016L
10k Ohm
1
28 27 26
68 UF 6v, +20%
SRAM Read
The CY22E016L performs a READ cycle whenever CE and OE are low while WE and HSB are high. The address specified on pins A0-10 determines which of the 2,048 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAA (READ cycle #1). If the READ is initiated by CE or OE, the outputs will be valid at tACE or at tDOE, whichever is later (READ cycle #2). The data outputs will repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and will remain valid until another address change or until CE or OE is brought high, or WE or HSB is brought low.
U 0.1 F Bypass
14
15
Figure 1. AutoStore(R) Mode
10k Ohm
10k Ohm
SRAM Write
A WRITE cycle is performed whenever CE and WE are low and HSB is high. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common I/O pins I/O0-7 will be written into the memory if it is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. It is recommended that OE be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If OE is left low, internal circuitry will turn off the output buffers tHZWE after WE goes low.
1
28 27 26
AutoStore Operation
During normal AutoStore operation, the CY22E016L will draw current from VCC to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation. After power up, when the voltage on the VCAP pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC and initiate a STORE operation. Figure 1 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor having a capacity of between 68 F and 220 F (20%) rated at 6V should be provided.In system power mode both VCC and VCAP are connected to the +5V power supply without the 68-F capacitor. In this mode the AutoStore function of the CY22E016L will operate on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the
14 15
U 0.1 F Bypass
Figure 2. System Power Mode If an automatic STORE on power loss is not required, then VCC can be tied to ground and +5V applied to VCAP. This is the AutoStore Inhibit mode, in which the AutoStore function is disabled. If the CY22E016L is operated in this configuration, references to VCC should be changed to VCAP throughout this data sheet. In this mode, STORE operations may be triggered with the HSB pin. It is not permissible to change between these three options "on the fly".
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10k Ohm
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PRELIMINARY
CY22E016L
10k Ohm
1
28 27 26
10k Ohm
be scaled by the number of devices connected to it. When any one of the CY22E016L detects a power loss and asserts HSB, the common HSB pin will cause all parts to request a STORE cycle (a STORE will take place in those CY22E016L that have been written since the last nonvolatile cycle). During any STORE operation, regardless of how it was initiated, the CY22E016L will continue to drive the HSB pin low, releasing it only when the STORE is complete. Upon completion of the STORE operation the CY22E016L will remain disabled until the HSB pin returns high. If HSB is not used, it should be left unconnected.
0.1U F Bypass
Hardware RECALL (Power-up)
During power-up, or after any low-power condition (VCC < VSWITCH), an internal RECALL request will be latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle will automatically be initiated and will take tHRECALL to complete.
Data Protection
14 15
Figure 3. AutoStore Inhibit Mode In order to prevent unneeded STORE operations, automatic STOREs as well as those initiated by externally driving HSB low will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. An optional pull-up resistor is shown connected to HSB. This can be used to signal the system that the AutoStore cycle is in progress.
The CY22E016L protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and WRITE operations. The low voltage condition is detected when VCC < VSWITCH. If the CY22E016L is in a WRITE mode (both CE and WE low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power-up or brown-out conditions.
Noise Considerations
The CY22E016L is a high-speed memory and so must have a high-frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
Hardware STORE (HSB) Operation
The CY22E016L provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the CY22E016L will conditionally initiate a STORE operation after tDELAY. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven low to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the CY22E016L will continue SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it will be allowed a time, tDELAY, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high. The HSB pin can be used to synchronize multiple CY22E016L while using a single larger capacitor. To operate in this mode the HSB pin should be connected together to the HSB pins from the other CY22E016L. An external pull-up resistor to +5V is required since HSB acts as an open-drain pull-down. The VCAP pins from the other CY22E016L parts can be tied together and share a single capacitor. The capacitor size must
Low Average Active Power
CMOS technology provides the CY22E016L the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 4 shows the relationship between ICC and READ/WRITE cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the CY22E016L depends on the following items: 1. The duty cycle of chip enable. 2. The overall cycle rate for accesses. 3. The ratio of READs to WRITEs. 4. CMOS vs. TTL Input Levels. 5. The operating temperature. 6. The VCC level. 7. I/O loading.
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PRELIMINARY
Preventing STOREs
The STORE function can be disabled on the fly by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, as it will have to overpower the internal pull-down device that drives HSB low for 20 ns at the onset of a STORE. Table 1. Hardware Mode Selection CE H L L X WE X H L X HSB H H H L A10-A0 X X X X Mode Not Selected Read SRAM Write SRAM Non-Volatile STORE I/O
CY22E016L
When the CY22E016L is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the CY22E016L will attempt to pull HSB low; if HSB doesn't actually get below VIL, the part will stop trying to pull HSB low and abort the STORE attempt.
Power Standby Active Active ICC2
Output High-Z Output Data Input Data Output High-Z
Figure 4. Current vs. Cycle Time (READ)
Figure 5. Current vs. Cycle Time (WRITE)
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PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC Relative to GND.......... -0.5V to 7.0V Voltage Applied to Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Input Voltage ............................................ -0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential...................-0.5V to VCC + 2.0V
CY22E016L
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [1] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 4.5V to 5.5V
DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V) [2]
Parameter ICC1 Description Average VCC Current Test Conditions tRC = 25 ns Commercial tRC = 35 ns tRC = 45 ns Dependent on output loading and cycle rate. Industrial Values obtained without output loads. IOUT = 0mA. All Inputs Don't Care, VCC = Max. Average current for duration tSTORE Min. Max. 85 75 65 75 3 10 Unit mA mA mA mA mA mA
ICC2 ICC3
Average VCC Current during STORE
Average VCC Current at WE > (VCC - 0.2). All other inputs cycling. tAVAV = 200 ns, 5V, 25C Dependent on output loading and cycle rate. Values obtained without output loads. typical Average VCAP Current All Inputs Don't Care, VCC = Max. during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0MHz. -1 -5 2.2 VSS - 0.5 IOUT = -4 mA except HSB IOUT = 8 mA except HSB IOUT = 3 mA 2.4 VCC = Max., VSS < VIN < VCC, CE or OE > VIH
ICC4 ISB
2 2.5
mA mA
IILK IOLK VIH VIL VOH VOL VBL
Input Leakage Current VCC = Max., VSS < VIN < VCC Off-State Output Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Logic "0" on HSB
+1 +5 VCC + 0.5 0.8 0.4 0.4
A A V V V V V
Capacitance [3]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Max. 8 7 Unit pF pF
Notes: 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 5V. Not 100% tested. 3. These parameters are guaranteed but not tested.
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PRELIMINARY
Thermal Resistance [3]
Parameter Description Test Conditions
CY22E016L
28-SOIC TBD TBD
Unit C/W C/W
JA JC
Thermal Resistance Test conditions follow standard test methods and proce(Junction to Ambient) dures for measuring thermal impedance, per EIA / JESD51. Thermal Resistance (Junction to Case)
AC Test Loads
R1 480 5.0V OUTPUT 30 pF R2 255
AC Test Conditions
Input Pulse Levels.................................................. 0 V to 3 V Input Rise and Fall Times (10% - 90%)........................ <5 ns Input and Output Timing Reference Levels....................1.5 V
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PRELIMINARY
AC Switching Characteristics
Parameter Cypress Alt. Parameter Parameter SRAM Read Cycle tACE tRC tAA
[4] [5]
CY22E016L
25ns part Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Set-Up to End of Write Data Hold After End of Write Address Set-Up to End of Write Address Set-Up to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write 5 25 20 20 10 0 20 0 0 10 0 25 0 10 5 5 10 25 25 10 Min. Max. 25
35ns part Min. Max. 35 35 35 15 5 5 13 0 13 0 35 35 25 25 12 0 25 0 0 13 5
45ns part Min. Max. 45 45 45 20 5 5 15 0 15 0 45 45 30 30 15 0 30 0 0 14 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW
[6]
tDOE tOHA [5] tLZCE [6] tHZCE tLZOE tPU [3] tPD
[ 3] [6] [6]
tHZOE [6]
SRAM Write Cycle tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE [6,7] tLZWE
AutoStore/Power-Up RECALL
CY22E016L Parameter tHRECALL [8] tSTORE tDELAY VSWITCH VRESET
[9]
Description Power-Up RECALL Duration STORE Cycle Duration Time allowed to complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level
Min.
Max. 550 10
Unit s ms s V V
1 4.0 4.5 3.6
Notes: 4. WE must be HIGH during SRAM Read Cycles. 5. Device is continuously selected with CE and OE both Low. 6. Measured 200 mV from steady state output voltage. 7. If WE is Low when CE goes Low, the outputs remain in the high-impedance state. 8. tHRECALL starts from the time VCC rises above VSWITCH. 9. If an SRAM Write has not taken place since the last non-volatile cycle, no STORE will take place.
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PRELIMINARY
Hardware STORE Cycle
CY22E016L
CY22E016L Parameter tSTORE [6] tDELAY tHLHX tHLBL
[10]
Description STORE Cycle Duration Time allowed to complete SRAM Cycle Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
Min 1
Max 10 700
Unit ms s ns ns ns
tRESTORE [11]
15 300
Switching Waveforms
tRC
ADDRESS
t AA t OH
DQ (DATA OUT) DATA VALID
Figure 6. SRAM Read Cycle #1: Address Controlled [4, 5, 12]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
DQ (DATA OUT)
tLZOE t PU
tDOE
DATA VALID
tHZOE
ACTIVE
ICC
STANDBY
Figure 7. SRAM Read Cycle #2: CE Controlled [4,12]
Notes: 10. Read and Write cycles in progress before HSB are given this amount of time to complete. 11. tRESTOREis only applicable after tSTORE is complete. 12. HSB must remain HIGH during READ and WRITE cycles.
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PRELIMINARY
Switching Waveforms (continued)
tWC
ADDRESS
CY22E016L
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 8. SRAM Write Cycle #1: WE Controlled [12,13]
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Figure 9. SRAM Write Cycle #2: CE Controlled
Note: 13. CE or WE must be > VIH during address transitions.
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PRELIMINARY
Switching Waveforms (continued)
CY22E016L
VCC VSWITCH VRESET
AutoStore
POWER-UP RECALL
tRESTORE
HSB
tVSBL tDELAY
tSTORE
DQ (DATA OUT)
POWER UP RECALL
(NO SRAM WRITES)
BROWN OUT NO STROKE
BROWN OUT AutoStore TM NO RECALL (VCC DID NOT GO BELOW VRESET)
BROWN OUT AutoStore TM RECALL WHEN VCC RETURNS ABOVE VSWITCH
NO RECALL (VCC DID NOT GO BELOW VRESET)
Figure 10. AutoStore/Power-Up RECALL
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PRELIMINARY
Switching Waveforms (continued)
tHLHX tSTORE
CY22E016L
HSB (IN)
HSB (OUT)
tHLBL
HIGH IMPEDANCE
HIGH IMPEDANCE
t DELAY
DQ (DATA OUT) DATA VALID DATA VALID
Figure 11. Hardware STORE Cycle
PART NUMBERING NOMENCLATURE CY 22 E 016 L- SZ 25 X C T
Option: T - Tape & Reel Blank - Std. Temperature: C - Commercial (0 to 70C) I - Industrial (-40C to 85C) Pb-Free Package: SZ - 28 SOIC Data Bus: L - x8 Density: 016 - 16 Kb Voltage: E - 5.0V Speed: 25 - 25 ns 35 - 35 ns 45 - 45 ns
NVSRAM 22 - AutoStore + Hardware Store
Cypress
Document #: 001-06727 Rev. *C
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PRELIMINARY
Ordering Information
Speed (ns) 25 35 35 45 Ordering Code CY22E016L-SZ25XCT CY22E016L-SZ35XCT CY22E016L-SZ35XIT CY22E016L-SZ45XCT Package Name 51-85026 51-85026 51-85026 51-85026 28-pin SOIC 28-pin SOIC 28-pin SOIC 28-pin SOIC Package Type
CY22E016L
Operating Range Commercial Commercial Industrial Commercial
All of the above mentioned parts are of "Lead-Free" type.
Package Diagrams
28-pin (300-Mil) Molded SOIC (51-85026)
NOTE :
PIN 1 ID
1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX.
14
1
0.291[7.39] 0.300[7.62]
4. PACKAGE WEIGHT 0.85gms
*
0.394[10.01] 0.419[10.64]
15
28
0.026[0.66] 0.032[0.81]
PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.
0.697[17.70] 0.713[18.11]
SEATING PLANE
0.092[2.33] 0.105[2.67] 0.004[0.10] 0.013[0.33] 0.050[1.27] TYP.
51-85026-*D
0.004[0.10] 0.0118[0.30]
*
0.019[0.48]
0.015[0.38] 0.050[1.27]
0.0091[0.23] 0.0125[3.17]
*
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation.All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06727 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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PRELIMINARY
Document History Page
Document Title: CY22E016L 16-Kbit (2K x 8) nvSRAM Document Number: 001-06727 REV. ** *A *B *C ECN NO. 427789 437321 472053 503290 Issue Date See ECN See ECN See ECN See ECN Orig. of Change TUP TUP TUP PCI New Data Sheet Show Data Sheet on external Web Description of Change
CY22E016L
Updated Part Numbering Nomenclatue and Ordering Information Converted from Advance to Preliminary Changed the term "Unlimited" to "Infinite" Removed Industrial Grade mention Corrected VIL min. spec from (VCC - 0.5) to (VSS - 0.5) Updated Part Nomenclature Table and Ordering InformationTable
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